1. Field of the Invention
This invention relates to the fabrication of large scale integrated circuits within a single semiconductor substrate. In particular, it relates to fabricating such devices having greatly reduced size.
2. Description of the Prior Art
A principal critical factor in designing the layouts of semiconductor chips is the power dissipation, which is the limiting factor both in the number of devices or circuits which may be contained within a chip of given size as well as the speed of operation of a given circuit. Generally speaking, the faster the circuit, the more power which is dissipated thereby. Additionally, the power dissipation is a direct function of the number of devices on a given chip.
One solution to this problem has long been recognized: reduce the size of the individual devices. Not only does this solution allow more transistors to be fabricated within a chip of a given size but it also lowers the parasitic capacitances of each device. This permits operation at a higher impedance level for a given operating speed, thereby resulting in lower power dissipation.
The problem of power dissipation is particularly severe in the design of vertical bipolar transistors of the planar type. However, it is also a factor to be considered in the design of both lateral bipolar transistors as well as field effect transistors.
With respect to vertical bipolar transistors it is critical that the base, collector reach-through and isolation regions be aligned properly; each of these regions is fabricated separately.
The definition of each of these impurity regions requires a separate masking operation. The formation of each region may include diffusion, ion implantation, dielectric isolation or combinations of these. Conventionally, the masking operations involve coating a suitable dielectric layer disposed on the substrate with a photoresist, exposing the photoresist actinically through a mask, developing the photoresist pattern defined by the mask, and etching the dielectric layer through the photoresist down to the semiconductor surface. Other techniques such as the use of E-beam resists and plasma etching are also becoming common-place.
As previously mentioned, the limiting factor in reducing the size of the regions and the distances between regions is the registration tolerance of the masks. Conventionally, each mask must be aligned perfectly with respect to the patterns formed by previous masks. Perfect alignment can never be assured; and tolerances, commonly termed design ground rules, must take this into account. This results in devices which have larger distances between adjacent regions than is necessary to satisfy circuit parameters.
Similar reasoning applies to any complex circuits using such devices as lateral bipolar transistors, complementary field effect transistors or other types of advanced devices.
Relatively recently, semiconductor designers have turned to the use of self-alignment masking techniques as a way of avoiding the need for perfect mask alignments at each step. U.S. Pat. Nos. 3,928,082, 3,948,694, 3,967,981 and 3,900,352, the last-mentioned being assigned to the same assignee as the present application, are examples of such self-aligned techniques. However, the manufacturing application of these processes is somewhat limited, either by the necessity for the ion implantation of one or more impurity regions through a mask or with respect to the number of impurity regions which may be self-aligned. For example, to our knowledge it has not been possible to "self-align" a dielectric isolation region either with respect to the base and collector contact regions of a bipolar transistor or with respect to the source, drain and substrate contacts of a field effect transistor.
Another problem apparently not fully appreciated by designers using prior art self-alignment techniques is the well known lateral undercutting of one masking layer which is disposed beneath another during an etching process. The undercut portion increases the effective masking window for impurities and could result in the overlapping of regions which should be spaced apart.